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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT40104 4-bit bidirectional universal shift register; 3-state Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 4-bit bidirectional universal shift register; 3-state FEATURES * Synchronous parallel or serial operating * 3-state outputs * Output capability: bus driver * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT40104 are high-speed Si-gate CMOS devices and are pin compatible with the "40104" of the "4000B" series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40104 are universal shift registers featuring parallel inputs, parallel outputs, shift-right and shift-left serial inputs and 3-state outputs allowing the devices to be used in bus-organized systems. 74HC/HCT40104 In the parallel-load mode (S0 and S1 are HIGH), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock input (CP). During loading, serial data flow is inhibited. Shift-right and shift-left are accomplished synchronously on the positive clock edge with serial data entered at the shift-right (DSR) and shift-left (DSL) serial inputs, respectively. Clearing the register is accomplished by setting both mode controls (S0 and S1) LOW and clocking the register. When the output enable input (OE) is LOW, all outputs assume the high-impedance OFF-state (Z). APPLICATIONS * Arithmetic unit bus registers * Serial/parallel conversion * General-purpose register for bus organized systems * General-purpose registers QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay CP to Qn maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 13 62 3.5 75 HCT 15 57 3.5 75 ns MHz pF pF UNIT December 1990 2 Philips Semiconductors Product specification 4-bit bidirectional universal shift register; 3-state PIN DESCRIPTION PIN NO. 1 2 3, 4, 5, 6 7 8 9, 10 11 15, 14, 13, 12 16 SYMBOL OE DSR D0 to D3 DSL GND S0, S1 CP Q0 to Q3 VCC NAME AND FUNCTION 74HC/HCT40104 3-state output enable input (active HIGH) serial data shift-right input parallel data inputs serial data shift-left input ground (0 V) mode control inputs clock input (LOW-to-HIGH, edge-triggered) 3-state parallel outputs positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification 4-bit bidirectional universal shift register; 3-state FUNCTION TABLE 74HC/HCT40104 INPUTS (OE = HIGH) OPERATING MODES reset shift left shift right parallel load Notes S1 S0 DSR DSL D0 to D3 X X X X X L H OUTPUTS at tn+1 Q0 Q1 Q2 Q3 L H H L L H H L L L H H H H X X X L H X X X L H X X X X L L L Q3 Q3 Q1 Q1 L H L L H Q2 Q2 L H Q1 Q 2 Q1 Q2 L H L H Q0 Q0 L H 1. H = HIGH voltage level L = LOW voltage level X = don't care tn+1 = state after next LOW-to-HIGH transition of CP Fig.4 Functional diagram. Fig.5 Logic diagram. December 1990 4 Philips Semiconductors Product specification 4-bit bidirectional universal shift register; 3-state DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 -40 to +85 -40 to +125 min. max. 255 51 43 225 45 38 225 45 38 90 18 15 120 24 20 120 24 20 120 24 20 2 2 2 2 2 2 4.0 20 24 74HC/HCT40104 TEST CONDITIONS UNIT V WAVEFORMS CC (V) ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 min. typ. max. min. max. tPHL/ tPLH propagation delay CP to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn output transition time 44 16 13 33 12 10 50 18 14 14 5 4 80 16 14 80 16 14 80 16 14 2 2 2 2 2 2 6.0 30 35 11 4 3 17 6 5 22 8 6 -8 -3 -2 -14 -5 -4 19 56 67 170 34 29 150 30 26 150 30 26 60 12 10 100 20 17 100 20 17 100 20 17 2 2 2 2 2 2 4.8 24 28 215 43 37 190 38 33 190 38 33 75 15 13 tPZH/ tPZL ns Fig.8 tPHZ/ tPLZ ns Fig.8 tTHL/ tTLH ns Fig.6 tW clock pulse width HIGH or LOW set-up time Dn, DSR, DSL to CP set-up time S0, S1 to CP hold time Dn, DSR, DSL to CP hold time S0, S1 to CP maximum clock pulse frequency ns Fig.6 tsu ns Fig.8 tsu ns Fig.8 th ns Fig.8 th ns Fig.8 fmax MHz Fig.6 December 1990 5 Philips Semiconductors Product specification 4-bit bidirectional universal shift register; 3-state DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI Note to HCT types 74HC/HCT40104 The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT D0 to D3 DSR, DSL CP S0, S1 OE UNIT LOAD COEFFICIENT 0.35 0.35 0.35 0.70 1.40 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 -40 to +85 -40 to +125 min. max. 51 45 53 18 24 24 30 2 2 18 ns ns ns ns ns ns ns ns ns MHz 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.6 Fig.8 Fig.8 Fig.6 Fig.6 Fig.8 Fig.8 Fig.8 Fig.8 Fig.6 UNIT V WAVEFORMS CC (V) TEST CONDITIONS min. typ. max. min. max. tPHL/ tPLH tPZH/ tPZL tPHZ/ tPLZ tTHL/ tTLH tW tsu tsu th th fmax propagation delay CP to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn output transition time clock pulse width HIGH or LOW set-up time Dn, DSR, DSL to CP set-up time S0, S1 to CP hold time Dn, DSR, DSL to CP hold time S0, S1 to CP maximum clock pulse frequency 16 16 20 2 2 27 18 12 21 5 7 8 9 -2 -5 52 34 30 35 12 20 20 25 2 2 22 43 38 44 15 December 1990 6 Philips Semiconductors Product specification 4-bit bidirectional universal shift register; 3-state AC WAVEFORMS 74HC/HCT40104 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the 3-state enable and disable times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the set-up and hold times from the Dn, DSR, DSL and Sn inputs to the clock (CP). December 1990 7 Philips Semiconductors Product specification 4-bit bidirectional universal shift register; 3-state PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". 74HC/HCT40104 December 1990 8 |
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